This invention relates to semiconductor processing and more particularly to a method for forming improved buried contacts in complementary MOS devices.
MOS devices arranged in complementary symmetry circuit configuration (hereinafter referred to as CMOS devices) are highly desirable to the design engineer due to the inherent noise immunity that they provide and the low power requirements associated therewith. However, as the density of the integrated circuit CMOS device on a given size chip is increased, the device size becomes so small that the contact area for the individual devices becomes disproportionately large and occupies a larger percentage of the chip real estate than is desired. Thus, if the contact area may be made smaller, the designer now has the opportunity to provide the chip with a higher density of CMOS devices.
The buried contact may be defined as a contact scheme which provides a direct connection between two polycrystalline silicon (polysilicon) layers or between a polysilicon layer and a layer of silicon with no appreciable penalty for either the misalignment or the junction formed at the point of connection. Where buried contacts are used in certain circuit configurations, that is when doped polysilicon lead lines are used with n-channel bulk silicon MOS devices, few difficulties are encountered since the bulk silicon and polysilicon lines are traditionally doped with n-type impurities. However, when processing CMOS devices where both n-channel and p-channel devices are used, there are no completely satisfactory prior art methods of interconnecting the devices with doped buried contacts without encountering the formation of an objectionable PN junction. This is due principally to the fact that regardless of the doping of the polysilicon line, one end of the line is connected to an N channel device while the other end terminates at a P channel device. For example, if an N-doped polysilicon line were used as an interconnect, N-P junction would be formed where the line terminated at the p-channel device. Similarly, when using a p-doped polysilicon line as the interconnection between a p-channel and an n-channel device, a PN junction would be formed between the interconnect and the n-channel device.
In a copending application filed by A. Dingwall on Oct. 3, 1978, Ser. No. 948,103 entitled "FIVE TRANSISTOR CMOS MEMORY CELL INCLUDING DIODES" and assigned to the same assignee as the subject application, the author acknowledges the presence of the diodes and devises a circuit which includes the diodes. One feature of the circuit is that there is sufficient drive to overcome the inherent voltage drop which may appear across the diodes.
In another application filed by D. Tanguay, et al. on Feb. 27, 1978, Ser. No. 881,255 entitled "BURIED CONTACT FOR COMPLEMENTARY MOS DEVICES" and assigned to the same assignee as the subject application. The inventors therein recognize the formation of an undesirable junction and, after the formation thereof provide another processing step to short circuit the undesired junction.
Still another pending application relating to the improvement of buried contacts is present in a pending application filed by C. E. Weitzel, et al. on Mar. 17, 1978, Ser. No. 887,724 entitled "LOW SURFACE RESISTANCE MOS/FET DEVICE AND METHOD OF MAKING SAME" in which the authors, in an endeavor to anticipate the possible formation of an undesired junction, completely silicide the surface of the area of the source and drain regions, so that when a subsequent doped polysilicon line is terminated thereon the low surface resistance presented by the silicided area will minimize the effect of the junction that might be formed.